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Faculty of Science, Technology & Environment - Staff

Mansour Assaf
Mansour Assaf
Job Info
Department:
School of Engineering and Physics
Position Title:
Associate Professor
Contact Info
Phone #:
+679 32 32593
Email:
Personal Info

Qualifications:
DPhil MApplSc Be'Sc Ott.

Biography:
Dr. Assaf joined The University of the South Pacific (USP) in 2010. Prior to USP, he was an Associate Professor of Centre for Information and Communications Technology, at The University of Trinidad and Tobago. Before that, he served as a Research Scholar and Lecturer at The School of Information Technology and Engineering (SITE) of the University of Ottawa (UOO), Ottawa, Ontario, Canada. He received his Ph.D. in Electrical and Computer Engineering from UOO where he also received his M.A.Sc. in Electrical Engineering and the B.A.Sc. degree in Telecommunications. He holds a B.Sc. degree in Applied Physics from The Lebanese University (LU). His research interests are in the areas of computer architecture, mixed-signal analysis, hardware/software co-design and test, fault-tolerant computing, distributed detection in sensor networks, and RFID technologies. Dr. Assaf is a senior member of the IEEE, and a member of the ACM. He received the 2003 IEEE Donald G. Fink Prize Paper Award.

Research Interests

  • Fault Tolerant Computing
  • Embedded Systems, Sensor Networks

Teaching

  • Computer Architecture, Mixed-signal Circuits
  • Signals and Systems, Digital Signal Processing
  • Embedded Systems, FPGA Design

Selected Publications

A. R. Applegate, S. R. Das, S. N. Biswas, A. Hossain, and M. H. Assaf, “Conditional Fault Detection Compatibility and Test Response Compaction with Array of Two-input Linear Logic”, The ATLAS T3 Annual Meeting Proceedings, June 2010.

M. H. Assaf, L-A. Moore, S. R. Das, E. M. Petriu, and S. N. Biswas, “IP Core Logic Fault Test Simulation Environment”, IEEE Instrumentation and Measurement Technology Conference, Austin, TX , May 3 – 6, 2010.

M. H. Assaf, K. Williams, and Z. Sakr, S. R. Das, S. Biswas, and E. M. Petriu, “RFID for the Optimization of the Public Transportation System”, IEEE Instrumentation and Measurement Technology Conference, Austin, TX, May 3 – 6, 2010.

M. H. Assaf, L-A. Moore, S. R. Das, E. M. Petriu, S. N. Biswas, and A. Hossain, ”Logic Fault Test Simulation Environment for IP Core-Based Digital Systems”, The 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009), Cancún, México, 2 – 5 August, 2009.

M. H. Assaf, and L-A. Moore, ”Low-level Logic Fault Test Environment for Embedded ASICs”, The 5th IEEE-GCC 2009-Control and Instrumentation Conference, Kuwait City, Kuwait, 17 – 19 March, 2009 (accepted for presentation).

S. R. Das, A. Hossain, J-F. Li, E. M. Petriu, S. N. Biswas, W-B. Jone, and M. H. Assaf, “Further Studies on Improved Test Efficiency in Cores-Based System-on-Chips Using ModelSim Verification Tool”, IEEE Instrumentation and Measurement Technology Conference, Singapore, May 5 – 7, 2009.

S. N. Biswas, S. R. Das, M. H. Assaf, and A. Hossain, “Test Vector Compression Technique in System-on-Chip”, IEEE Instrumentation and Measurement Technology Conference, Singapore, May 5 – 7, 2009.

S. R. Das; A. Hossain; S. Biswas; E. M. Petriu, M. H. Assaf; W. B. Jone; and M. Sahinoglu, “On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing”, IEEE Transactions on Instrumentation and Measurement, Vol. 57,  Issue 10,  October 2008.

M. H. Assaf, and M. Fathi, ”Built-In Hardware for Analog Circuitry Testing”, CERMA 2008 – The Electronics, Robotics and Automotive Mechanics Conference Technology Conference, Cuernavaca, Morelos, Mexico, September 30 – October 03, 2008.

S. N. Biswas, N. Emerole, S. R. Das, M. H. Assaf, “Software Based Self Testing Hybrid Technique for Test Vector Compression“, IDPT 2008, Integrated Design and Process Technology Conference, June 1 – 6, 2008.

M. H. Assaf, S. R. Das, W. Hermas, E. M. Petriu, and S. Biswas, “Verification of Ethernet IP Core MAC Design Using Deterministic Test Methodology”, IEEE Instrumentation and Measurement Technology Conference, Victoria, BC, Canada, May 12 – 15, 2008.

M. H. Assaf, S. Khan, and S. R. Das, “Energy Efficient Optimization of Wireless Embedded Sensor Networks“, IDPT 2008, Integrated Design and Process Technology Conference, June 1 – 6, 2008.

S. R. Das, J.-F. Li, A. Hossain, A. R. Nayak, E. M. Petriu, S. N. Biswas, M. H. Assaf,  W.-B. Jone, and M. Sahinoglu, “Testing Cores-Based System-on-Chips Using Modelsim Verification Tool“,IDPT 2008, Integrated Design and Process Technology Conference, June 1 – 6, 2008.

M. H. Assaf, S. R. Das, W. Hermas and W-B. Jone,”Promising Complex ASIC Design Verification Methodology”, IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, May 1 – 3, 2007.

M. H. Assaf, A. Rajesh, “General Architecture and Instruction Set Enhancements for Multimedia Applications”, The 11th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, FL, U.S.A., July 8 – 11, 2007.

Das, S. R.; Mukherjee, S.; Petriu, E. M.; Assaf, M. H; Hossain, A., “Space Compaction for Embedded Cores-Based System-on-Chips (SOCs) Using Fault Graded Output Merger”, IEEE Instrumentation and Measurement Technology Conference Proceedings, Warsaw, 2007 IEEE 1 – 3 May 2007.

V. Groza; R. Abielmona; M. H. Assaf; M. Elbadri; M. El-Kadri; A. Khalaf, “A Self-Reconfigurable Platform for Built-In Self-Test Applications”, IEEE Transactions on Instrumentation and Measurement, Vol. 56, Issue 4, August 2007.

S. R. Das; J. Zakizadeh; S. Biswas; M. H. Assaf; A. R. Nayak; E. M. Petriu; W. B. Jone; and M. Sahinoglu, “Testing Analog and Mixed-Signal Circuits With Built-In Hardware—A New Approach”, IEEE  Transactions on Instrumentation and Measurement Vol. 56,  Issue 3,  June 2007.

A. Rajesh; and M. H. Assaf, “General Architecture and Instruction Set Enhancements for Multimedia Applications”, The Journal on Systemics, Cybernetics and Informatics (JSCI) Vol. 5,  Issue 6,  2007.

M. H. Assaf, M. El-Kadri, V. Groza, “Digital Core Testing Environment Executed on an Embedded RTOS/MicoBlaze Softcore Processor”, The 10th World Multi-Conference on Systemics, Cybernetics and Informatics, pp. 107-111, Orlando, FL, U.S.A., July 16 – 19, 2006.

S.R. Das, S. Mukherjee, E.M. Petriu, M. H. Assaf, M. Sahinoglu, W.-B. Jone, “An Improved Fault Simulation Approach Based on Verilog With Application to ISCAS Benchmark Circuits,” Proc. IMTC/2006, IEEE Instrumentation Measurement Technology Conference, Sorrento, Italy, April 2006.

S. R. Das, C. V. Ramamoorthy, M. H. Assaf, E. M. Petriu, and W. -B. Jone: A novel approach to designing aliasing-free space compactors based on switching theory formulation, IEEE Transactions on Instrumentation and Measurement, Vol. 54, No. 3, June 2005.

M. H Assaf, R. S. Abielmona, P. Abolghasem, S. R. Das, E. M. Petriu, and V. Groza : Built-in self-test for digital IP cores using a reconfigurable FPGA device, Presented at the 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, FL, U.S.A., July 10-13, 2005 (Conference Proceedings, pp. 129-135).

J. Zakizadeh, S.R. Das, M.H. Assaf, E.M. Petriu, M. Sahinoglu, W-B. Jone. Testing Analog and Mixed-Signal Circuits with Built-In Hardware - A New Approach, Proc. IMTC/2005, IEEE Instr. Meas. Technol. Conf., May 2005 pp. 166-171.

S. R. Das, C. V. Ramamoorthy, M. H. Assaf, E. M. Petriu, and W. -B. Jone: A novel approach to designing aliasing-free space compactors based on switching theory formulation, IEEE Transactions on Instrumentation and Measurement, Vol. 54, No. 3,June 2005.

M. H Assaf, R. S. Abielmona, P. Abolghasem, S. R. Das, E. M. Petriu, and V. Groza : Built-in self-test for digital IP cores using a reconfigurable FPGA device, Presented at the 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, FL, U.S.A., July 10-13, 2005 (Conference Proceedings, pp. 129-135).

J. Zakizadeh, S.R. Das, M.H. Assaf, E.M. Petriu, M. Sahinoglu, W-B. Jone. Testing Analog and Mixed-Signal Circuits with Built-In Hardware - A New Approach, Proc. IMTC/2005, IEEE Instr. Meas. Technol. Conf., May 2005 pp. 166-171.

M. H. Assaf, S. R. Das, E. M. Petriu, Liwu Jin, Chuan Jin, Dhruv Biswas, Voicu Groza, and Mehmet Sahinoglu : Hardware and Software Co-Design in Space Compaction of Cores-Based Digital Circuits, IEEE Instrumentation and Measurement Technology Conference, Como, Italy, May 18-20, 2004.

S. R. Das, M. H. Assaf, E. M. Petriu, and M. Sahinoglu: Aliasing-free compaction in testing cores-based system-on-chip (SOC) using compatibility of response data outputs, Transactions of the SDPS, Vol. 8, March 2004, pp. 1-17.

S. R. Das, C. V. Ramamoorthy, M. H. Assaf, E. M. Petriu and W. B. Jone: Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities, IEEE Transactions on Instrumentation and Measurement, Vol. 50, No. 6, December 2001, pp. 1725-1747 - Recipient of IEEE Donald Fink Prize Paper Award for 2003.

Publications in USP Electronic Research Repository
 


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